A Test Strategy for Nanoscale Wafer Level Packaged Circuits

This paper presents a strategy for testing future generations of wafer-level packaged logic devices that have nanoscale I/O structures. The strategy assumes that the devices incorporate built-in self test (BIST) features so that only a subset of the functional I/O needs to be directly accessed during testing. A miniature tester is described that provides test control, pattern sequencing, and critical timing for the test. An interposer is used for electro-mechanical connection between the miniature tester and the device I/O nanostructures. Prototypes of the miniature tester are presented that demonstrate the fundamental ability to control logic transitions with 20ps or better accuracy, as is required to meet the test needs for 5 Gbps signals. A complete 5 Gbps miniature tester is under development using the results obtained in the prototyping phases of the project.